Questions about transceiver's serial interface

[mersault]

Hi,

Seeing the CSK Motherboard's and PPM D1's datasheets I got a question. In CSK motherboard's datasheet appears that pin H1.17 and H1.18 are implemented for the communication with the transceiver (also, they are mapped in the PIC24 pins 49 and 50) but a few pages below it says that pins H1.39 and H1.40 are also for the communication with the transceiver (TXD_MHX and RXD_MHX) but they are not mapped in the PPM connector, so there's no connection with the PIC24. Are the pins H1.17 and H1.18 connected to the H1.39 and H1.40 respectively? If not, How Can I communicate with the transceiver if the pins are not connected to the PIC?

Thank you very much.

Bets regards.

[Andrew]

Refer to the Motherboard (MB) or Development Board (DB) schematics and PPM schematics.

TXD_MHX & RXD_MHX (and the other _MHX signals) are directly connected to the MHX socket, and operate over ([PWR_MHX, 0V]).

When the MHX is ON (-ON_MHX active) and the MHX level shifter/isolator between the PPM processor and the MHX is enabled (-OE_MHX is active), then the Tx and Rx pins from/to the PPM processor appear -- level-shifted from [VCC, 0V] to [PWR_MHX, 0V] -- at the MHX. This is how the PPM processor drives the MHX directly, given that they can and normally do operate at different voltages. You can see this in action in the Test\Test1 example application. Similarly, the various flow control signals (HS[5..0]) make their way from the PPM processor to the MHX through these level shifters / isolators. These level shifters achieve zero-=power isolation across different voltages.

Therefore, the answer to

Are the pins H1.17 and H1.18 connected to the H1.39 and H1.40 respectively?

is No, at least, never directly.

So, why are -RST_MHX through RXD_MHX on the CSK Bus? They're there so that another processor (with signals running at [PWR_MHX,0]) can talk directly to the MHX. To do this, PWR_MHX must have ... wait for it .. power , and the isolators on the MB should not be enabled -- this latter condition is controlled entirely by the MB, whereas the former can be done by either having the MB force -ON_MHX active, OR by feeding PWR_MHX directly via the CSK Bus.

IOW, the CSk architecture has ways for a PPM processor to talk to the MHX, or for something on the CSK Bus to talk to the MHX, or even both, if the user arbitrates it all ...