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Top speed for SPI communications?

Discussions pertaining to the electrical issues (e.g. circuitry, power, etc.) of Pumpkin's CubeSat kit.

Top speed for SPI communications?

Postby z_sat » Tue Jun 15, 2010 11:31 am


I'm using the CSK Dev board with a msp430f1611 (w/ Salvo RTOS) and I'm running into some issues with the maximum transfer speed with SPI through UART0. I am using XT2CLK (7.3MHz crystal) for SMCLK and choosing BRCLK to use SMCLK with a divisor of 2. Other relevant SPI registers below:

Code: Select all

  BCSCTL2 |= SELS;                     // SMCLK = XTAL2 (7.3728MHz)

  ME1 |= USPIE0;          //Enable Module 
  U0CTL |= CHAR + SYNC + MM + SWRST;          //SPI, 8-bit data, synchronous mode, master, SWRST
  U0TCTL |= CKPH + SSEL1 + SSEL0 + STC;          //Use SMCLK for BRCLK, Normal clock phase, 3-pin SPI mode
  U0BR0 = 0x02;          //Max clock frequency of bus (BRCLK/2)
  U0BR1 = 0x00;
  U0MCTL = 0x00;          //Modulation control not used

  U0CTL &= ~SWRST;          // Initialize USART state machine
  //IE1 = UTXIE0 + URXIE0;          //Enable TX and RX interrupts

  P3SEL |= BIT1 + BIT2 + BIT3;          //this should set up SPI0 to P3_1:3
  P3DIR |= BIT0;          //Set P3.0 to be GPO to be used for CS in SPI mode
  P3OUT |= SPI_CS;          //initial state is not selected

I configured all registers to the theoretical maximum SPI clock rate BRCLK/2 (~3.6MHz). Whenever I write to TXBUF0, the data frame shows up twice on the logic analyzer that I am using. I am able to verify that the clock rate is in fact ~3.6MHz. However, when I back the SPI clock rate down to BRCLK/8, the frame only shows up once as it should.

Does anyone have any insight as to what is happening?


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