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Questions re Differences between Revs C and D

Discussions pertaining to the electrical issues (e.g. circuitry, power, etc.) of Pumpkin's CubeSat kit.

Questions re Differences between Revs C and D

Postby Unregistered User » Fri May 15, 2009 10:21 am

Also is there any change in the CubeSAT bus pin configuration of rev C and rev D w.r.t I2C pins? Specifically, we recognize that some pins on the MSP430 itself have moved, which will cause them to move on the the CubeSat bus on the RevC Development board. How have these pins been resolved in the Rev D? Have the lines been reconfigured on the PPM (A3) and similarly on the target board on the RevD Development board, so that the lines do not move in the CubeSat bus. In this case, redesigning the target board for the Rev C development board should be able to put the pins back where they would be in the Bus. Can you confirm that this is indeed the case, and if possible provide us with a list of the lines that have moved on the development board's target board?
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Re: Questions re Differences between Revs C and D

Postby aek » Fri May 15, 2009 10:46 am

The pin-to-pin mapping between the 64-pin MSP430s ('1612, '1611, now also '2618) and the CubeSat Kit Bus has not changed from Rev A through Rev D.

The nomenclature has changed, since the MSP430 is no longer the only processor we support. E.g. an MSP430's P3.0 appears as IO.0 on its Rev D PPM module, and on the Rev D Motherboard CubeSat Kit Bus connectors.

Revs A through C had no explicit support for I2C, and no I2C peripherals as part of Pumpkin-suppled hardware. Rev C onwards did have two signals (SCL_SYS and SDA_SYS) dedicated to I2C on the CubeSat Kit Bus connectors. With Rev C, it was at the users' discretion as to how they would implement I2C connections. One possibility was to use USART0 solely for I2C, with I2C lines emanating from P3.1 & P3.3. Another possibility was to use some sort of I2C isolator to connect the MSP430's I2C lines to SCL_SYS and SDA_SYS, which would otherwise have been left isolated.

From Rev D onwards, each PPM (e.g. PPM A1) connects the processor to the SCL_SYS and SDA_SYS lines in a "best possible" manner. For the '1611 and '1612 (PPM A2 and PPM A1, respectively), a PCA9515A I2C isolator is used to route the MSP430's sole SCL and SDA lines to SCL_SYS and SDA_SYS, active when IO.0 (-CS_SD/ON_I2C) is HIGH. IN ALL OF THESE CASES, THE MSP430's USART0:I2C PERIPHERAL CANNOT BE USED AT THE SAME TIME AS ITS USART0:UART OR USART0:SPI PERIPHERAL, because they are all part of the same peripheral (USART0).

For the '2618 (PPM A3), the situation is a bit better. The '2618 has the more sophisticated USCI peripheral, which can supply both a UART and an I2C at the same time. To maintain maximum compatibility with PPM A1 and A2, PPM A3 also uses the PCA9515A, and routes UCB0SCL and UCB0SDA to the PCA9515A. This is the delivered configuration.

PPM A3 can also be user-configured in an alternate (and some would say better) way:
by routing UCB1SCL directly to SCL_SYS, and UCB1SDA to SDA_SYS, with no PCA9515A used (see schematics). This configuration also requires a change in some of the resistors fitted.

The MSP-TS430PM64 Adapter on each Rev D Dev Board that is in a CubeSatKit /MSP430 has jumpers to enable any of these different MSP430 I2C configurations.

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[This message has been edited by aek (to reflect the current shipping configuration of PPM A3).]

[This message has been edited by aek (edited May 19, 2009).]

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